Process Technology

Early 2010s: Full-scale use of FinFETs has started

Planar FETs in CMOS logic LSIs have been scaled down to 45nm and 32nm nodes by adopting strained silicon channels and HK/MG (High-k/Metal Gate), but it has become more difficult to suppress the short channel effect at 22nm node. As for the 22nm node, TSMC and UMC adopted planar FETs, while GlobalFoundries and Samsung adopted PD-SOI FETs, which were developed from XMOS Transistors invented by Hayashi and Sekikawa (Electrotechnical Laboratory), and Intel adopted FinFETs invented by Hisamoto (Hitachi) and others. The era of three-dimensional structure FETs began. In the 16nm node, TSMC and Samsung also adopted FinFETs, and FinFETs have become the mainstream of FETs in CMOS logic LSIs in the 2010s.

Schematic of FinFET Structure

Cross-sectional photo of FinFET and pattern photo of SRAM using FinFET