31) NEC Obtained the Exclusive License of Planar Patent in Japan

 
Photo A: Chip pattern of an initial planar type transistor produced by Fairchild Semiconductor


Photo B: Members of Fairchild Semiconductor at that time Noyce
(4th person from left) and Hoerni (2nd person from right)

At Fairchild Semiconductor founded in 1957 in the US, a person called Jean Hoerni was doing a work like icing a 3-layer cake. (translator’s note: n-p-n/p-n-p 3-layer) (quoted from the book titled "The Chip – How Two Americans Invented the Microchip and Launched a Revolution" written by T. R. Reid).
Mesa type transistor structure, which was then regarded as the final shape of transistor structure, was taken over into silicon era, and the production increased gradually. But this structure’s weakness was its high sensitivity to surface contamination.
Hoerni proposed a theoretical solution on this problem in 1958 which was to cover the surface with oxide, which could then protect the inside from contamination without any characteristics change. He named this process as “planar process”, because flat plane of silicon dioxide was formed on the surface of the chip. Photo A shows a chip pattern of initial planar type transistor produced by Fairchild Semiconductor. Since the pattern looked like a tear drop, it was called "Tear-drop."
This planar process later became IC’s basic technology, and became an important intellectual property of Fairchild Semiconductor. Robert Noyce, a key personnel of the company and the developer of "Planar IC" had negotiations with NEC through long-time acquainted Hiroe Osafune, and Fairchild Semiconductor finally granted the exclusive license of planar patent in Japan to NEC. Fairchild initially requested for 7% of license fee, but finally agreed with 4.5% in 1962.
Photo B shows Noyce (4th person from left) and Hoerni (2nd person from right)
(Source: US Fairchild Semiconductor)

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“Mr. Shimura’s Essays with Historic Photos”    Semiconductor History Museum of Japan
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